// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  vpc_top_nmanager_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 14:40:32 Create file
// ******************************************************************************

#ifndef __VPC_TOP_NMANAGER_C_UNION_DEFINE_H__
#define __VPC_TOP_NMANAGER_C_UNION_DEFINE_H__

/* Define the union U_VPC_CONTROL_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_0          : 31  ; /* [31:1] */
        unsigned int    vpc_rdma_start : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_CONTROL_1;

/* Define the union U_VPC_CONTROL_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_1            : 15  ; /* [31:17] */
        unsigned int    rdma_cvdr_rd_sel : 1  ; /* [16] */
        unsigned int    vcpi_axi_od_cfg  : 5  ; /* [15:11] */
        unsigned int    vcpi_axi_stop_ok : 1  ; /* [10] */
        unsigned int    vcpi_axi_stop_en : 1  ; /* [9] */
        unsigned int    in_bitwidth_cfg  : 1  ; /* [8] */
        unsigned int    rsv_2            : 5  ; /* [7:3] */
        unsigned int    in_format_cfg    : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_CONTROL_2;

/* Define the union U_VPC_CONTROL_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_3                  : 15  ; /* [31:17] */
        unsigned int    vpc_force_clk_on       : 1  ; /* [16] */
        unsigned int    rsv_4                  : 14  ; /* [15:2] */
        unsigned int    vcpi_hfbcd_clk_gt_en   : 1  ; /* [1] */
        unsigned int    rdma_linebuf_clk_gt_en : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_CONTROL_3;

/* Define the union U_VPC_RDMA_HADDR1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vcpi_srcyh_addr : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_HADDR1;

/* Define the union U_VPC_RDMA_HADDR2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vcpi_srcch_addr : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_HADDR2;

/* Define the union U_VPC_RDMA_HSTRIDE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vcpi_srcch_stride : 16  ; /* [31:16] */
        unsigned int    vcpi_srcyh_stride : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_HSTRIDE;

/* Define the union U_VPC_RDMA_PADDR1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vcpi_srcy_addr : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_PADDR1;

/* Define the union U_VPC_RDMA_PADDR2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vcpi_srcc_addr : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_PADDR2;

/* Define the union U_VPC_RDMA_PSTRIDE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    vcpi_srcc_stride : 16  ; /* [31:16] */
        unsigned int    vcpi_srcy_stride : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_PSTRIDE;

/* Define the union U_VPC_RDMA_PIC_SIZE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_5              : 3  ; /* [31:29] */
        unsigned int    vcpi_imgheight_pix : 13  ; /* [28:16] */
        unsigned int    rsv_6              : 3  ; /* [15:13] */
        unsigned int    vcpi_imgwidth_pix  : 13  ; /* [12:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_PIC_SIZE;

/* Define the union U_VPC_INT_STATUS1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_7                  : 8  ; /* [31:24] */
        unsigned int    vpc_cvdr_vp_wr_eol_sta : 5  ; /* [23:19] */
        unsigned int    vpc_cvdr_vp_wr_eof_sta : 5  ; /* [18:14] */
        unsigned int    vpc_cvdr_vp_wr_sof_sta : 5  ; /* [13:9] */
        unsigned int    vpc_cvdr_vp_rd_eol_sta : 3  ; /* [8:6] */
        unsigned int    vpc_cvdr_vp_rd_eof_sta : 3  ; /* [5:3] */
        unsigned int    vpc_cvdr_vp_rd_sof_sta : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_STATUS1;

/* Define the union U_VPC_INT_STATUS2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_8                      : 19  ; /* [31:13] */
        unsigned int    vpc_eof_int1_sta           : 1  ; /* [12] */
        unsigned int    vpc_eof_int2_sta           : 1  ; /* [11] */
        unsigned int    vpc_rdma_frame_end_sta     : 1  ; /* [10] */
        unsigned int    vpc_pipe_postcrop2_eop_sta : 1  ; /* [9] */
        unsigned int    vpc_pipe_yuvscale2_eof_sta : 1  ; /* [8] */
        unsigned int    vpc_pipe_yuvscale2_sof_sta : 1  ; /* [7] */
        unsigned int    vpc_pipe_postcrop1_eop_sta : 1  ; /* [6] */
        unsigned int    vpc_pipe_yuvscale_eof_sta  : 1  ; /* [5] */
        unsigned int    vpc_pipe_yuvscale_sof_sta  : 1  ; /* [4] */
        unsigned int    vpc_pipe_prescale3_sof_sta : 1  ; /* [3] */
        unsigned int    vpc_pipe_prescale2_sof_sta : 1  ; /* [2] */
        unsigned int    vpc_pipe_prescale1_sof_sta : 1  ; /* [1] */
        unsigned int    vpc_pipe_precrop_eop_sta   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_STATUS2;

/* Define the union U_VPC_INT_MASK1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_9                   : 8  ; /* [31:24] */
        unsigned int    vpc_cvdr_vp_wr_eol_mask : 5  ; /* [23:19] */
        unsigned int    vpc_cvdr_vp_wr_eof_mask : 5  ; /* [18:14] */
        unsigned int    vpc_cvdr_vp_wr_sof_mask : 5  ; /* [13:9] */
        unsigned int    vpc_cvdr_vp_rd_eol_mask : 3  ; /* [8:6] */
        unsigned int    vpc_cvdr_vp_rd_eof_mask : 3  ; /* [5:3] */
        unsigned int    vpc_cvdr_vp_rd_sof_mask : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_MASK1;

/* Define the union U_VPC_INT_MASK2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_10                      : 19  ; /* [31:13] */
        unsigned int    vpc_eof_int1_mask           : 1  ; /* [12] */
        unsigned int    vpc_eof_int2_mask           : 1  ; /* [11] */
        unsigned int    vpc_rdma_frame_end_mask     : 1  ; /* [10] */
        unsigned int    vpc_pipe_postcrop2_eop_mask : 1  ; /* [9] */
        unsigned int    vpc_pipe_yuvscale2_eof_mask : 1  ; /* [8] */
        unsigned int    vpc_pipe_yuvscale2_sof_mask : 1  ; /* [7] */
        unsigned int    vpc_pipe_postcrop1_eop_mask : 1  ; /* [6] */
        unsigned int    vpc_pipe_yuvscale_eof_mask  : 1  ; /* [5] */
        unsigned int    vpc_pipe_yuvscale_sof_mask  : 1  ; /* [4] */
        unsigned int    vpc_pipe_prescale3_sof_mask : 1  ; /* [3] */
        unsigned int    vpc_pipe_prescale2_sof_mask : 1  ; /* [2] */
        unsigned int    vpc_pipe_prescale1_sof_mask : 1  ; /* [1] */
        unsigned int    vpc_pipe_precrop_eop_mask   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_MASK2;

/* Define the union U_VPC_INT_MASK_STATUS1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_11                      : 8  ; /* [31:24] */
        unsigned int    vpc_cvdr_vp_wr_eol_mask_sta : 5  ; /* [23:19] */
        unsigned int    vpc_cvdr_vp_wr_eof_mask_sta : 5  ; /* [18:14] */
        unsigned int    vpc_cvdr_vp_wr_sof_mask_sta : 5  ; /* [13:9] */
        unsigned int    vpc_cvdr_vp_rd_eol_mask_sta : 3  ; /* [8:6] */
        unsigned int    vpc_cvdr_vp_rd_eof_mask_sta : 3  ; /* [5:3] */
        unsigned int    vpc_cvdr_vp_rd_sof_mask_sta : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_MASK_STATUS1;

/* Define the union U_VPC_INT_MASK_STATUS2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_12                          : 19  ; /* [31:13] */
        unsigned int    vpc_eof_int1_mask_sta           : 1  ; /* [12] */
        unsigned int    vpc_eof_int2_mask_sta           : 1  ; /* [11] */
        unsigned int    vpc_rdma_frame_end_mask_sta     : 1  ; /* [10] */
        unsigned int    vpc_pipe_postcrop2_eop_mask_sta : 1  ; /* [9] */
        unsigned int    vpc_pipe_yuvscale2_eof_mask_sta : 1  ; /* [8] */
        unsigned int    vpc_pipe_yuvscale2_sof_mask_sta : 1  ; /* [7] */
        unsigned int    vpc_pipe_postcrop1_eop_mask_sta : 1  ; /* [6] */
        unsigned int    vpc_pipe_yuvscale_eof_mask_sta  : 1  ; /* [5] */
        unsigned int    vpc_pipe_yuvscale_sof_mask_sta  : 1  ; /* [4] */
        unsigned int    vpc_pipe_prescale3_sof_mask_sta : 1  ; /* [3] */
        unsigned int    vpc_pipe_prescale2_sof_mask_sta : 1  ; /* [2] */
        unsigned int    vpc_pipe_prescale1_sof_mask_sta : 1  ; /* [1] */
        unsigned int    vpc_pipe_precrop_eop_mask_sta   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_MASK_STATUS2;

/* Define the union U_VPC_INT_CLR1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_13                 : 8  ; /* [31:24] */
        unsigned int    vpc_cvdr_vp_wr_eol_clr : 5  ; /* [23:19] */
        unsigned int    vpc_cvdr_vp_wr_eof_clr : 5  ; /* [18:14] */
        unsigned int    vpc_cvdr_vp_wr_sof_clr : 5  ; /* [13:9] */
        unsigned int    vpc_cvdr_vp_rd_eol_clr : 3  ; /* [8:6] */
        unsigned int    vpc_cvdr_vp_rd_eof_clr : 3  ; /* [5:3] */
        unsigned int    vpc_cvdr_vp_rd_sof_clr : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_CLR1;

/* Define the union U_VPC_INT_CLR2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_14                     : 19  ; /* [31:13] */
        unsigned int    vpc_eof_int1_clr           : 1  ; /* [12] */
        unsigned int    vpc_eof_int2_clr           : 1  ; /* [11] */
        unsigned int    vpc_rdma_frame_end_clr     : 1  ; /* [10] */
        unsigned int    vpc_pipe_postcrop2_eop_clr : 1  ; /* [9] */
        unsigned int    vpc_pipe_yuvscale2_eof_clr : 1  ; /* [8] */
        unsigned int    vpc_pipe_yuvscale2_sof_clr : 1  ; /* [7] */
        unsigned int    vpc_pipe_postcrop1_eop_clr : 1  ; /* [6] */
        unsigned int    vpc_pipe_yuvscale_eof_clr  : 1  ; /* [5] */
        unsigned int    vpc_pipe_yuvscale_sof_clr  : 1  ; /* [4] */
        unsigned int    vpc_pipe_prescale3_sof_clr : 1  ; /* [3] */
        unsigned int    vpc_pipe_prescale2_sof_clr : 1  ; /* [2] */
        unsigned int    vpc_pipe_prescale1_sof_clr : 1  ; /* [1] */
        unsigned int    vpc_pipe_precrop_eop_clr   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_CLR2;

/* Define the union U_VPC_INT_SET1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_15                 : 8  ; /* [31:24] */
        unsigned int    vpc_cvdr_vp_wr_eol_set : 5  ; /* [23:19] */
        unsigned int    vpc_cvdr_vp_wr_eof_set : 5  ; /* [18:14] */
        unsigned int    vpc_cvdr_vp_wr_sof_set : 5  ; /* [13:9] */
        unsigned int    vpc_cvdr_vp_rd_eol_set : 3  ; /* [8:6] */
        unsigned int    vpc_cvdr_vp_rd_eof_set : 3  ; /* [5:3] */
        unsigned int    vpc_cvdr_vp_rd_sof_set : 3  ; /* [2:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_SET1;

/* Define the union U_VPC_INT_SET2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_16                     : 19  ; /* [31:13] */
        unsigned int    vpc_eof_int1_set           : 1  ; /* [12] */
        unsigned int    vpc_eof_int2_set           : 1  ; /* [11] */
        unsigned int    vpc_rdma_frame_end_set     : 1  ; /* [10] */
        unsigned int    vpc_pipe_postcrop2_eop_set : 1  ; /* [9] */
        unsigned int    vpc_pipe_yuvscale2_eof_set : 1  ; /* [8] */
        unsigned int    vpc_pipe_yuvscale2_sof_set : 1  ; /* [7] */
        unsigned int    vpc_pipe_postcrop1_eop_set : 1  ; /* [6] */
        unsigned int    vpc_pipe_yuvscale_eof_set  : 1  ; /* [5] */
        unsigned int    vpc_pipe_yuvscale_sof_set  : 1  ; /* [4] */
        unsigned int    vpc_pipe_prescale3_sof_set : 1  ; /* [3] */
        unsigned int    vpc_pipe_prescale2_sof_set : 1  ; /* [2] */
        unsigned int    vpc_pipe_prescale1_sof_set : 1  ; /* [1] */
        unsigned int    vpc_pipe_precrop_eop_set   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_INT_SET2;

/* Define the union U_EOF_INT1_MERGE_ENABLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_17                          : 20  ; /* [31:12] */
        unsigned int    vpc_rdma_frame_end_mint1_en     : 1  ; /* [11] */
        unsigned int    vpc_pipe_postcrop2_eop_mint1_en : 1  ; /* [10] */
        unsigned int    vpc_pipe_yuvscale2_eof_mint1_en : 1  ; /* [9] */
        unsigned int    vpc_pipe_postcrop1_eop_mint1_en : 1  ; /* [8] */
        unsigned int    vpc_pipe_yuvscale_eof_mint1_en  : 1  ; /* [7] */
        unsigned int    vpc_pipe_precrop_eop_mint1_en   : 1  ; /* [6] */
        unsigned int    vpc_cvdr_vp_wr_eof_mint1_en     : 4  ; /* [5:2] */
        unsigned int    vpc_cvdr_vp_rd_eof_mint1_en     : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_EOF_INT1_MERGE_ENABLE;

/* Define the union U_EOF_INT2_MERGE_ENABLE */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_18                          : 20  ; /* [31:12] */
        unsigned int    vpc_rdma_frame_end_mint2_en     : 1  ; /* [11] */
        unsigned int    vpc_pipe_postcrop2_eop_mint2_en : 1  ; /* [10] */
        unsigned int    vpc_pipe_yuvscale2_eof_mint2_en : 1  ; /* [9] */
        unsigned int    vpc_pipe_postcrop1_eop_mint2_en : 1  ; /* [8] */
        unsigned int    vpc_pipe_yuvscale_eof_mint2_en  : 1  ; /* [7] */
        unsigned int    vpc_pipe_precrop_eop_mint2_en   : 1  ; /* [6] */
        unsigned int    vpc_cvdr_vp_wr_eof_mint2_en     : 4  ; /* [5:2] */
        unsigned int    vpc_cvdr_vp_rd_eof_mint2_en     : 2  ; /* [1:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_EOF_INT2_MERGE_ENABLE;

/* Define the union U_CMDLIST_IN_INT_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_19                     : 30  ; /* [31:2] */
        unsigned int    vpc_eof_int1_sta_cmdlst_en : 1  ; /* [1] */
        unsigned int    vpc_eof_int2_sta_cmdlst_en : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_CMDLIST_IN_INT_CTRL;

/* Define the union U_VPC_ERR_INT_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_20                       : 21  ; /* [31:11] */
        unsigned int    vpc_s2p_even_width_err_sta   : 1  ; /* [10] */
        unsigned int    vpc_cvdr_axi_rd_resp_err_sta : 1  ; /* [9] */
        unsigned int    vpc_cvdr_axi_wr_resp_err_sta : 1  ; /* [8] */
        unsigned int    vpc_cvdr_axi_wr_full_sta     : 1  ; /* [7] */
        unsigned int    vpc_cvdr_vp_wr_dropped_sta   : 5  ; /* [6:2] */
        unsigned int    vpc_rdma_axi_rd_resp_err_sta : 1  ; /* [1] */
        unsigned int    vpc_rdma_hfbcd_dec_err_sta   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_ERR_INT_STATUS;

/* Define the union U_VPC_ERR_INT_MASK */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_21                        : 21  ; /* [31:11] */
        unsigned int    vpc_s2p_even_width_err_mask   : 1  ; /* [10] */
        unsigned int    vpc_cvdr_axi_rd_resp_err_mask : 1  ; /* [9] */
        unsigned int    vpc_cvdr_axi_wr_resp_err_mask : 1  ; /* [8] */
        unsigned int    vpc_cvdr_axi_wr_full_mask     : 1  ; /* [7] */
        unsigned int    vpc_cvdr_vp_wr_dropped_mask   : 5  ; /* [6:2] */
        unsigned int    vpc_rdma_axi_rd_resp_err_mask : 1  ; /* [1] */
        unsigned int    vpc_rdma_hfbcd_dec_err_mask   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_ERR_INT_MASK;

/* Define the union U_VPC_ERR_INT_MASK_STATUS */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_22                            : 21  ; /* [31:11] */
        unsigned int    vpc_s2p_even_width_err_mask_sta   : 1  ; /* [10] */
        unsigned int    vpc_cvdr_axi_rd_resp_err_mask_sta : 1  ; /* [9] */
        unsigned int    vpc_cvdr_axi_wr_resp_err_mask_sta : 1  ; /* [8] */
        unsigned int    vpc_cvdr_axi_wr_full_mask_sta     : 1  ; /* [7] */
        unsigned int    vpc_cvdr_vp_wr_dropped_mask_sta   : 5  ; /* [6:2] */
        unsigned int    vpc_rdma_axi_rd_resp_err_mask_sta : 1  ; /* [1] */
        unsigned int    vpc_rdma_hfbcd_dec_err_mask_sta   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_ERR_INT_MASK_STATUS;

/* Define the union U_VPC_ERR_INT_CLR */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_23                       : 21  ; /* [31:11] */
        unsigned int    vpc_s2p_even_width_err_clr   : 1  ; /* [10] */
        unsigned int    vpc_cvdr_axi_rd_resp_err_clr : 1  ; /* [9] */
        unsigned int    vpc_cvdr_axi_wr_resp_err_clr : 1  ; /* [8] */
        unsigned int    vpc_cvdr_axi_wr_full_clr     : 1  ; /* [7] */
        unsigned int    vpc_cvdr_vp_wr_dropped_clr   : 5  ; /* [6:2] */
        unsigned int    vpc_rdma_axi_rd_resp_err_clr : 1  ; /* [1] */
        unsigned int    vpc_rdma_hfbcd_dec_err_clr   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_ERR_INT_CLR;

/* Define the union U_VPC_ERR_INT_SET */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_24                       : 21  ; /* [31:11] */
        unsigned int    vpc_s2p_even_width_err_set   : 1  ; /* [10] */
        unsigned int    vpc_cvdr_axi_rd_resp_err_set : 1  ; /* [9] */
        unsigned int    vpc_cvdr_axi_wr_resp_err_set : 1  ; /* [8] */
        unsigned int    vpc_cvdr_axi_wr_full_set     : 1  ; /* [7] */
        unsigned int    vpc_cvdr_vp_wr_dropped_set   : 5  ; /* [6:2] */
        unsigned int    vpc_rdma_axi_rd_resp_err_set : 1  ; /* [1] */
        unsigned int    vpc_rdma_hfbcd_dec_err_set   : 1  ; /* [0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_ERR_INT_SET;

/* Define the union U_VPC_BUS_CTRL_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_awaddr_ext : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_1;

/* Define the union U_VPC_BUS_CTRL_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_araddr_ext : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_2;

/* Define the union U_VPC_BUS_CTRL_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_awuser_l : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_3;

/* Define the union U_VPC_BUS_CTRL_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_awuser_m : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_4;

/* Define the union U_VPC_BUS_CTRL_5 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_awuser_h : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_5;

/* Define the union U_VPC_BUS_CTRL_6 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_aruser_l : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_6;

/* Define the union U_VPC_BUS_CTRL_7 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_aruser_m : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_7;

/* Define the union U_VPC_BUS_CTRL_8 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_aruser_h : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_8;

/* Define the union U_VPC_BUS_CTRL_9 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_25       : 6  ; /* [31:26] */
        unsigned int    cfg_arqos_en : 1  ; /* [25] */
        unsigned int    cfg_awqos_en : 1  ; /* [24] */
        unsigned int    cfg_arqos    : 4  ; /* [23:20] */
        unsigned int    cfg_awqos    : 4  ; /* [19:16] */
        unsigned int    rsv_26       : 4  ; /* [15:12] */
        unsigned int    cfg_arcache  : 4  ; /* [11:8] */
        unsigned int    rsv_27       : 4  ; /* [7:4] */
        unsigned int    cfg_awcache  : 4  ; /* [3:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_9;

/* Define the union U_VPC_BUS_CTRL_10 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    cfg_shim_ctrl : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_BUS_CTRL_10;

/* Define the union U_VPC_RDMA_DEBUG_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    hfbcd_debug_out1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_DEBUG_1;

/* Define the union U_VPC_RDMA_DEBUG_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    hfbcd_debug_out2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_RDMA_DEBUG_2;

/* Define the union U_VPC_LINEBUF_DEBUG_1 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    linebuf_debug_info1 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_LINEBUF_DEBUG_1;

/* Define the union U_VPC_LINEBUF_DEBUG_2 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    linebuf_debug_info2 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_LINEBUF_DEBUG_2;

/* Define the union U_VPC_LINEBUF_DEBUG_3 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    linebuf_debug_info3 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_LINEBUF_DEBUG_3;

/* Define the union U_VPC_LINEBUF_DEBUG_4 */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    linebuf_debug_info4 : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_LINEBUF_DEBUG_4;

/* Define the union U_VPC_CMDLST_DEBUG */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    rsv_28           : 16  ; /* [31:16] */
        unsigned int    cmdlst_debug_out : 16  ; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_CMDLST_DEBUG;

/* Define the union U_VPC_SP_RAM_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    sp_ram_ctrl : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_SP_RAM_CTRL;

/* Define the union U_VPC_TP_RAM_CTRL */
typedef union
{
    /* Define the struct bits */
    struct
    {
        unsigned int    tp_ram_ctrl : 32  ; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    unsigned int    u32;

} U_VPC_TP_RAM_CTRL;


//==============================================================================
/* Define the global struct */
typedef struct
{
    volatile U_VPC_CONTROL_1           VPC_CONTROL_1           ; /* 0 */
    volatile U_VPC_CONTROL_2           VPC_CONTROL_2           ; /* 4 */
    volatile U_VPC_CONTROL_3           VPC_CONTROL_3           ; /* 8 */
    volatile U_VPC_RDMA_HADDR1         VPC_RDMA_HADDR1         ; /* C */
    volatile U_VPC_RDMA_HADDR2         VPC_RDMA_HADDR2         ; /* 10 */
    volatile U_VPC_RDMA_HSTRIDE        VPC_RDMA_HSTRIDE        ; /* 14 */
    volatile U_VPC_RDMA_PADDR1         VPC_RDMA_PADDR1         ; /* 18 */
    volatile U_VPC_RDMA_PADDR2         VPC_RDMA_PADDR2         ; /* 1C */
    volatile U_VPC_RDMA_PSTRIDE        VPC_RDMA_PSTRIDE        ; /* 20 */
    volatile U_VPC_RDMA_PIC_SIZE       VPC_RDMA_PIC_SIZE       ; /* 24 */
    volatile U_VPC_INT_STATUS1         VPC_INT_STATUS1         ; /* 28 */
    volatile U_VPC_INT_STATUS2         VPC_INT_STATUS2         ; /* 2C */
    volatile U_VPC_INT_MASK1           VPC_INT_MASK1           ; /* 30 */
    volatile U_VPC_INT_MASK2           VPC_INT_MASK2           ; /* 34 */
    volatile U_VPC_INT_MASK_STATUS1    VPC_INT_MASK_STATUS1    ; /* 38 */
    volatile U_VPC_INT_MASK_STATUS2    VPC_INT_MASK_STATUS2    ; /* 3C */
    volatile U_VPC_INT_CLR1            VPC_INT_CLR1            ; /* 40 */
    volatile U_VPC_INT_CLR2            VPC_INT_CLR2            ; /* 44 */
    volatile U_VPC_INT_SET1            VPC_INT_SET1            ; /* 48 */
    volatile U_VPC_INT_SET2            VPC_INT_SET2            ; /* 4C */
    volatile U_EOF_INT1_MERGE_ENABLE   EOF_INT1_MERGE_ENABLE   ; /* 50 */
    volatile U_EOF_INT2_MERGE_ENABLE   EOF_INT2_MERGE_ENABLE   ; /* 54 */
    volatile U_CMDLIST_IN_INT_CTRL     CMDLIST_IN_INT_CTRL     ; /* 58 */
    volatile U_VPC_ERR_INT_STATUS      VPC_ERR_INT_STATUS      ; /* 5C */
    volatile U_VPC_ERR_INT_MASK        VPC_ERR_INT_MASK        ; /* 60 */
    volatile U_VPC_ERR_INT_MASK_STATUS VPC_ERR_INT_MASK_STATUS ; /* 64 */
    volatile U_VPC_ERR_INT_CLR         VPC_ERR_INT_CLR         ; /* 68 */
    volatile U_VPC_ERR_INT_SET         VPC_ERR_INT_SET         ; /* 6C */
    volatile U_VPC_BUS_CTRL_1          VPC_BUS_CTRL_1          ; /* 70 */
    volatile U_VPC_BUS_CTRL_2          VPC_BUS_CTRL_2          ; /* 74 */
    volatile U_VPC_BUS_CTRL_3          VPC_BUS_CTRL_3          ; /* 78 */
    volatile U_VPC_BUS_CTRL_4          VPC_BUS_CTRL_4          ; /* 7C */
    volatile U_VPC_BUS_CTRL_5          VPC_BUS_CTRL_5          ; /* 80 */
    volatile U_VPC_BUS_CTRL_6          VPC_BUS_CTRL_6          ; /* 84 */
    volatile U_VPC_BUS_CTRL_7          VPC_BUS_CTRL_7          ; /* 88 */
    volatile U_VPC_BUS_CTRL_8          VPC_BUS_CTRL_8          ; /* 8C */
    volatile U_VPC_BUS_CTRL_9          VPC_BUS_CTRL_9          ; /* 90 */
    volatile U_VPC_BUS_CTRL_10         VPC_BUS_CTRL_10         ; /* 94 */
    volatile U_VPC_RDMA_DEBUG_1        VPC_RDMA_DEBUG_1        ; /* 98 */
    volatile U_VPC_RDMA_DEBUG_2        VPC_RDMA_DEBUG_2        ; /* 9C */
    volatile U_VPC_LINEBUF_DEBUG_1     VPC_LINEBUF_DEBUG_1     ; /* A0 */
    volatile U_VPC_LINEBUF_DEBUG_2     VPC_LINEBUF_DEBUG_2     ; /* A4 */
    volatile U_VPC_LINEBUF_DEBUG_3     VPC_LINEBUF_DEBUG_3     ; /* A8 */
    volatile U_VPC_LINEBUF_DEBUG_4     VPC_LINEBUF_DEBUG_4     ; /* AC */
    volatile U_VPC_CMDLST_DEBUG        VPC_CMDLST_DEBUG        ; /* B0 */
    volatile U_VPC_SP_RAM_CTRL         VPC_SP_RAM_CTRL         ; /* B4 */
    volatile U_VPC_TP_RAM_CTRL         VPC_TP_RAM_CTRL         ; /* B8 */

} S_vpc_top_nmanager_REGS_TYPE;

/* Declare the struct pointor of the module vpc_top_nmanager */
extern volatile S_vpc_top_nmanager_REGS_TYPE *gopvpc_top_nmanagerAllReg;

/* Declare the functions that set the member value */
int iSetVPC_CONTROL_1_vpc_rdma_start(unsigned int uvpc_rdma_start);
int iSetVPC_CONTROL_2_rdma_cvdr_rd_sel(unsigned int urdma_cvdr_rd_sel);
int iSetVPC_CONTROL_2_vcpi_axi_od_cfg(unsigned int uvcpi_axi_od_cfg);
int iSetVPC_CONTROL_2_vcpi_axi_stop_ok(unsigned int uvcpi_axi_stop_ok);
int iSetVPC_CONTROL_2_vcpi_axi_stop_en(unsigned int uvcpi_axi_stop_en);
int iSetVPC_CONTROL_2_in_bitwidth_cfg(unsigned int uin_bitwidth_cfg);
int iSetVPC_CONTROL_2_in_format_cfg(unsigned int uin_format_cfg);
int iSetVPC_CONTROL_3_vpc_force_clk_on(unsigned int uvpc_force_clk_on);
int iSetVPC_CONTROL_3_vcpi_hfbcd_clk_gt_en(unsigned int uvcpi_hfbcd_clk_gt_en);
int iSetVPC_CONTROL_3_rdma_linebuf_clk_gt_en(unsigned int urdma_linebuf_clk_gt_en);
int iSetVPC_RDMA_HADDR1_vcpi_srcyh_addr(unsigned int uvcpi_srcyh_addr);
int iSetVPC_RDMA_HADDR2_vcpi_srcch_addr(unsigned int uvcpi_srcch_addr);
int iSetVPC_RDMA_HSTRIDE_vcpi_srcch_stride(unsigned int uvcpi_srcch_stride);
int iSetVPC_RDMA_HSTRIDE_vcpi_srcyh_stride(unsigned int uvcpi_srcyh_stride);
int iSetVPC_RDMA_PADDR1_vcpi_srcy_addr(unsigned int uvcpi_srcy_addr);
int iSetVPC_RDMA_PADDR2_vcpi_srcc_addr(unsigned int uvcpi_srcc_addr);
int iSetVPC_RDMA_PSTRIDE_vcpi_srcc_stride(unsigned int uvcpi_srcc_stride);
int iSetVPC_RDMA_PSTRIDE_vcpi_srcy_stride(unsigned int uvcpi_srcy_stride);
int iSetVPC_RDMA_PIC_SIZE_vcpi_imgheight_pix(unsigned int uvcpi_imgheight_pix);
int iSetVPC_RDMA_PIC_SIZE_vcpi_imgwidth_pix(unsigned int uvcpi_imgwidth_pix);
int iSetVPC_INT_STATUS1_vpc_cvdr_vp_wr_eol_sta(unsigned int uvpc_cvdr_vp_wr_eol_sta);
int iSetVPC_INT_STATUS1_vpc_cvdr_vp_wr_eof_sta(unsigned int uvpc_cvdr_vp_wr_eof_sta);
int iSetVPC_INT_STATUS1_vpc_cvdr_vp_wr_sof_sta(unsigned int uvpc_cvdr_vp_wr_sof_sta);
int iSetVPC_INT_STATUS1_vpc_cvdr_vp_rd_eol_sta(unsigned int uvpc_cvdr_vp_rd_eol_sta);
int iSetVPC_INT_STATUS1_vpc_cvdr_vp_rd_eof_sta(unsigned int uvpc_cvdr_vp_rd_eof_sta);
int iSetVPC_INT_STATUS1_vpc_cvdr_vp_rd_sof_sta(unsigned int uvpc_cvdr_vp_rd_sof_sta);
int iSetVPC_INT_STATUS2_vpc_eof_int1_sta(unsigned int uvpc_eof_int1_sta);
int iSetVPC_INT_STATUS2_vpc_eof_int2_sta(unsigned int uvpc_eof_int2_sta);
int iSetVPC_INT_STATUS2_vpc_rdma_frame_end_sta(unsigned int uvpc_rdma_frame_end_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_postcrop2_eop_sta(unsigned int uvpc_pipe_postcrop2_eop_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_yuvscale2_eof_sta(unsigned int uvpc_pipe_yuvscale2_eof_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_yuvscale2_sof_sta(unsigned int uvpc_pipe_yuvscale2_sof_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_postcrop1_eop_sta(unsigned int uvpc_pipe_postcrop1_eop_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_yuvscale_eof_sta(unsigned int uvpc_pipe_yuvscale_eof_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_yuvscale_sof_sta(unsigned int uvpc_pipe_yuvscale_sof_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_prescale3_sof_sta(unsigned int uvpc_pipe_prescale3_sof_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_prescale2_sof_sta(unsigned int uvpc_pipe_prescale2_sof_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_prescale1_sof_sta(unsigned int uvpc_pipe_prescale1_sof_sta);
int iSetVPC_INT_STATUS2_vpc_pipe_precrop_eop_sta(unsigned int uvpc_pipe_precrop_eop_sta);
int iSetVPC_INT_MASK1_vpc_cvdr_vp_wr_eol_mask(unsigned int uvpc_cvdr_vp_wr_eol_mask);
int iSetVPC_INT_MASK1_vpc_cvdr_vp_wr_eof_mask(unsigned int uvpc_cvdr_vp_wr_eof_mask);
int iSetVPC_INT_MASK1_vpc_cvdr_vp_wr_sof_mask(unsigned int uvpc_cvdr_vp_wr_sof_mask);
int iSetVPC_INT_MASK1_vpc_cvdr_vp_rd_eol_mask(unsigned int uvpc_cvdr_vp_rd_eol_mask);
int iSetVPC_INT_MASK1_vpc_cvdr_vp_rd_eof_mask(unsigned int uvpc_cvdr_vp_rd_eof_mask);
int iSetVPC_INT_MASK1_vpc_cvdr_vp_rd_sof_mask(unsigned int uvpc_cvdr_vp_rd_sof_mask);
int iSetVPC_INT_MASK2_vpc_eof_int1_mask(unsigned int uvpc_eof_int1_mask);
int iSetVPC_INT_MASK2_vpc_eof_int2_mask(unsigned int uvpc_eof_int2_mask);
int iSetVPC_INT_MASK2_vpc_rdma_frame_end_mask(unsigned int uvpc_rdma_frame_end_mask);
int iSetVPC_INT_MASK2_vpc_pipe_postcrop2_eop_mask(unsigned int uvpc_pipe_postcrop2_eop_mask);
int iSetVPC_INT_MASK2_vpc_pipe_yuvscale2_eof_mask(unsigned int uvpc_pipe_yuvscale2_eof_mask);
int iSetVPC_INT_MASK2_vpc_pipe_yuvscale2_sof_mask(unsigned int uvpc_pipe_yuvscale2_sof_mask);
int iSetVPC_INT_MASK2_vpc_pipe_postcrop1_eop_mask(unsigned int uvpc_pipe_postcrop1_eop_mask);
int iSetVPC_INT_MASK2_vpc_pipe_yuvscale_eof_mask(unsigned int uvpc_pipe_yuvscale_eof_mask);
int iSetVPC_INT_MASK2_vpc_pipe_yuvscale_sof_mask(unsigned int uvpc_pipe_yuvscale_sof_mask);
int iSetVPC_INT_MASK2_vpc_pipe_prescale3_sof_mask(unsigned int uvpc_pipe_prescale3_sof_mask);
int iSetVPC_INT_MASK2_vpc_pipe_prescale2_sof_mask(unsigned int uvpc_pipe_prescale2_sof_mask);
int iSetVPC_INT_MASK2_vpc_pipe_prescale1_sof_mask(unsigned int uvpc_pipe_prescale1_sof_mask);
int iSetVPC_INT_MASK2_vpc_pipe_precrop_eop_mask(unsigned int uvpc_pipe_precrop_eop_mask);
int iSetVPC_INT_MASK_STATUS1_vpc_cvdr_vp_wr_eol_mask_sta(unsigned int uvpc_cvdr_vp_wr_eol_mask_sta);
int iSetVPC_INT_MASK_STATUS1_vpc_cvdr_vp_wr_eof_mask_sta(unsigned int uvpc_cvdr_vp_wr_eof_mask_sta);
int iSetVPC_INT_MASK_STATUS1_vpc_cvdr_vp_wr_sof_mask_sta(unsigned int uvpc_cvdr_vp_wr_sof_mask_sta);
int iSetVPC_INT_MASK_STATUS1_vpc_cvdr_vp_rd_eol_mask_sta(unsigned int uvpc_cvdr_vp_rd_eol_mask_sta);
int iSetVPC_INT_MASK_STATUS1_vpc_cvdr_vp_rd_eof_mask_sta(unsigned int uvpc_cvdr_vp_rd_eof_mask_sta);
int iSetVPC_INT_MASK_STATUS1_vpc_cvdr_vp_rd_sof_mask_sta(unsigned int uvpc_cvdr_vp_rd_sof_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_eof_int1_mask_sta(unsigned int uvpc_eof_int1_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_eof_int2_mask_sta(unsigned int uvpc_eof_int2_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_rdma_frame_end_mask_sta(unsigned int uvpc_rdma_frame_end_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_postcrop2_eop_mask_sta(unsigned int uvpc_pipe_postcrop2_eop_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_yuvscale2_eof_mask_sta(unsigned int uvpc_pipe_yuvscale2_eof_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_yuvscale2_sof_mask_sta(unsigned int uvpc_pipe_yuvscale2_sof_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_postcrop1_eop_mask_sta(unsigned int uvpc_pipe_postcrop1_eop_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_yuvscale_eof_mask_sta(unsigned int uvpc_pipe_yuvscale_eof_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_yuvscale_sof_mask_sta(unsigned int uvpc_pipe_yuvscale_sof_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_prescale3_sof_mask_sta(unsigned int uvpc_pipe_prescale3_sof_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_prescale2_sof_mask_sta(unsigned int uvpc_pipe_prescale2_sof_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_prescale1_sof_mask_sta(unsigned int uvpc_pipe_prescale1_sof_mask_sta);
int iSetVPC_INT_MASK_STATUS2_vpc_pipe_precrop_eop_mask_sta(unsigned int uvpc_pipe_precrop_eop_mask_sta);
int iSetVPC_INT_CLR1_vpc_cvdr_vp_wr_eol_clr(unsigned int uvpc_cvdr_vp_wr_eol_clr);
int iSetVPC_INT_CLR1_vpc_cvdr_vp_wr_eof_clr(unsigned int uvpc_cvdr_vp_wr_eof_clr);
int iSetVPC_INT_CLR1_vpc_cvdr_vp_wr_sof_clr(unsigned int uvpc_cvdr_vp_wr_sof_clr);
int iSetVPC_INT_CLR1_vpc_cvdr_vp_rd_eol_clr(unsigned int uvpc_cvdr_vp_rd_eol_clr);
int iSetVPC_INT_CLR1_vpc_cvdr_vp_rd_eof_clr(unsigned int uvpc_cvdr_vp_rd_eof_clr);
int iSetVPC_INT_CLR1_vpc_cvdr_vp_rd_sof_clr(unsigned int uvpc_cvdr_vp_rd_sof_clr);
int iSetVPC_INT_CLR2_vpc_eof_int1_clr(unsigned int uvpc_eof_int1_clr);
int iSetVPC_INT_CLR2_vpc_eof_int2_clr(unsigned int uvpc_eof_int2_clr);
int iSetVPC_INT_CLR2_vpc_rdma_frame_end_clr(unsigned int uvpc_rdma_frame_end_clr);
int iSetVPC_INT_CLR2_vpc_pipe_postcrop2_eop_clr(unsigned int uvpc_pipe_postcrop2_eop_clr);
int iSetVPC_INT_CLR2_vpc_pipe_yuvscale2_eof_clr(unsigned int uvpc_pipe_yuvscale2_eof_clr);
int iSetVPC_INT_CLR2_vpc_pipe_yuvscale2_sof_clr(unsigned int uvpc_pipe_yuvscale2_sof_clr);
int iSetVPC_INT_CLR2_vpc_pipe_postcrop1_eop_clr(unsigned int uvpc_pipe_postcrop1_eop_clr);
int iSetVPC_INT_CLR2_vpc_pipe_yuvscale_eof_clr(unsigned int uvpc_pipe_yuvscale_eof_clr);
int iSetVPC_INT_CLR2_vpc_pipe_yuvscale_sof_clr(unsigned int uvpc_pipe_yuvscale_sof_clr);
int iSetVPC_INT_CLR2_vpc_pipe_prescale3_sof_clr(unsigned int uvpc_pipe_prescale3_sof_clr);
int iSetVPC_INT_CLR2_vpc_pipe_prescale2_sof_clr(unsigned int uvpc_pipe_prescale2_sof_clr);
int iSetVPC_INT_CLR2_vpc_pipe_prescale1_sof_clr(unsigned int uvpc_pipe_prescale1_sof_clr);
int iSetVPC_INT_CLR2_vpc_pipe_precrop_eop_clr(unsigned int uvpc_pipe_precrop_eop_clr);
int iSetVPC_INT_SET1_vpc_cvdr_vp_wr_eol_set(unsigned int uvpc_cvdr_vp_wr_eol_set);
int iSetVPC_INT_SET1_vpc_cvdr_vp_wr_eof_set(unsigned int uvpc_cvdr_vp_wr_eof_set);
int iSetVPC_INT_SET1_vpc_cvdr_vp_wr_sof_set(unsigned int uvpc_cvdr_vp_wr_sof_set);
int iSetVPC_INT_SET1_vpc_cvdr_vp_rd_eol_set(unsigned int uvpc_cvdr_vp_rd_eol_set);
int iSetVPC_INT_SET1_vpc_cvdr_vp_rd_eof_set(unsigned int uvpc_cvdr_vp_rd_eof_set);
int iSetVPC_INT_SET1_vpc_cvdr_vp_rd_sof_set(unsigned int uvpc_cvdr_vp_rd_sof_set);
int iSetVPC_INT_SET2_vpc_eof_int1_set(unsigned int uvpc_eof_int1_set);
int iSetVPC_INT_SET2_vpc_eof_int2_set(unsigned int uvpc_eof_int2_set);
int iSetVPC_INT_SET2_vpc_rdma_frame_end_set(unsigned int uvpc_rdma_frame_end_set);
int iSetVPC_INT_SET2_vpc_pipe_postcrop2_eop_set(unsigned int uvpc_pipe_postcrop2_eop_set);
int iSetVPC_INT_SET2_vpc_pipe_yuvscale2_eof_set(unsigned int uvpc_pipe_yuvscale2_eof_set);
int iSetVPC_INT_SET2_vpc_pipe_yuvscale2_sof_set(unsigned int uvpc_pipe_yuvscale2_sof_set);
int iSetVPC_INT_SET2_vpc_pipe_postcrop1_eop_set(unsigned int uvpc_pipe_postcrop1_eop_set);
int iSetVPC_INT_SET2_vpc_pipe_yuvscale_eof_set(unsigned int uvpc_pipe_yuvscale_eof_set);
int iSetVPC_INT_SET2_vpc_pipe_yuvscale_sof_set(unsigned int uvpc_pipe_yuvscale_sof_set);
int iSetVPC_INT_SET2_vpc_pipe_prescale3_sof_set(unsigned int uvpc_pipe_prescale3_sof_set);
int iSetVPC_INT_SET2_vpc_pipe_prescale2_sof_set(unsigned int uvpc_pipe_prescale2_sof_set);
int iSetVPC_INT_SET2_vpc_pipe_prescale1_sof_set(unsigned int uvpc_pipe_prescale1_sof_set);
int iSetVPC_INT_SET2_vpc_pipe_precrop_eop_set(unsigned int uvpc_pipe_precrop_eop_set);
int iSetEOF_INT1_MERGE_ENABLE_vpc_rdma_frame_end_mint1_en(unsigned int uvpc_rdma_frame_end_mint1_en);
int iSetEOF_INT1_MERGE_ENABLE_vpc_pipe_postcrop2_eop_mint1_en(unsigned int uvpc_pipe_postcrop2_eop_mint1_en);
int iSetEOF_INT1_MERGE_ENABLE_vpc_pipe_yuvscale2_eof_mint1_en(unsigned int uvpc_pipe_yuvscale2_eof_mint1_en);
int iSetEOF_INT1_MERGE_ENABLE_vpc_pipe_postcrop1_eop_mint1_en(unsigned int uvpc_pipe_postcrop1_eop_mint1_en);
int iSetEOF_INT1_MERGE_ENABLE_vpc_pipe_yuvscale_eof_mint1_en(unsigned int uvpc_pipe_yuvscale_eof_mint1_en);
int iSetEOF_INT1_MERGE_ENABLE_vpc_pipe_precrop_eop_mint1_en(unsigned int uvpc_pipe_precrop_eop_mint1_en);
int iSetEOF_INT1_MERGE_ENABLE_vpc_cvdr_vp_wr_eof_mint1_en(unsigned int uvpc_cvdr_vp_wr_eof_mint1_en);
int iSetEOF_INT1_MERGE_ENABLE_vpc_cvdr_vp_rd_eof_mint1_en(unsigned int uvpc_cvdr_vp_rd_eof_mint1_en);
int iSetEOF_INT2_MERGE_ENABLE_vpc_rdma_frame_end_mint2_en(unsigned int uvpc_rdma_frame_end_mint2_en);
int iSetEOF_INT2_MERGE_ENABLE_vpc_pipe_postcrop2_eop_mint2_en(unsigned int uvpc_pipe_postcrop2_eop_mint2_en);
int iSetEOF_INT2_MERGE_ENABLE_vpc_pipe_yuvscale2_eof_mint2_en(unsigned int uvpc_pipe_yuvscale2_eof_mint2_en);
int iSetEOF_INT2_MERGE_ENABLE_vpc_pipe_postcrop1_eop_mint2_en(unsigned int uvpc_pipe_postcrop1_eop_mint2_en);
int iSetEOF_INT2_MERGE_ENABLE_vpc_pipe_yuvscale_eof_mint2_en(unsigned int uvpc_pipe_yuvscale_eof_mint2_en);
int iSetEOF_INT2_MERGE_ENABLE_vpc_pipe_precrop_eop_mint2_en(unsigned int uvpc_pipe_precrop_eop_mint2_en);
int iSetEOF_INT2_MERGE_ENABLE_vpc_cvdr_vp_wr_eof_mint2_en(unsigned int uvpc_cvdr_vp_wr_eof_mint2_en);
int iSetEOF_INT2_MERGE_ENABLE_vpc_cvdr_vp_rd_eof_mint2_en(unsigned int uvpc_cvdr_vp_rd_eof_mint2_en);
int iSetCMDLIST_IN_INT_CTRL_vpc_eof_int1_sta_cmdlst_en(unsigned int uvpc_eof_int1_sta_cmdlst_en);
int iSetCMDLIST_IN_INT_CTRL_vpc_eof_int2_sta_cmdlst_en(unsigned int uvpc_eof_int2_sta_cmdlst_en);
int iSetVPC_ERR_INT_STATUS_vpc_s2p_even_width_err_sta(unsigned int uvpc_s2p_even_width_err_sta);
int iSetVPC_ERR_INT_STATUS_vpc_cvdr_axi_rd_resp_err_sta(unsigned int uvpc_cvdr_axi_rd_resp_err_sta);
int iSetVPC_ERR_INT_STATUS_vpc_cvdr_axi_wr_resp_err_sta(unsigned int uvpc_cvdr_axi_wr_resp_err_sta);
int iSetVPC_ERR_INT_STATUS_vpc_cvdr_axi_wr_full_sta(unsigned int uvpc_cvdr_axi_wr_full_sta);
int iSetVPC_ERR_INT_STATUS_vpc_cvdr_vp_wr_dropped_sta(unsigned int uvpc_cvdr_vp_wr_dropped_sta);
int iSetVPC_ERR_INT_STATUS_vpc_rdma_axi_rd_resp_err_sta(unsigned int uvpc_rdma_axi_rd_resp_err_sta);
int iSetVPC_ERR_INT_STATUS_vpc_rdma_hfbcd_dec_err_sta(unsigned int uvpc_rdma_hfbcd_dec_err_sta);
int iSetVPC_ERR_INT_MASK_vpc_s2p_even_width_err_mask(unsigned int uvpc_s2p_even_width_err_mask);
int iSetVPC_ERR_INT_MASK_vpc_cvdr_axi_rd_resp_err_mask(unsigned int uvpc_cvdr_axi_rd_resp_err_mask);
int iSetVPC_ERR_INT_MASK_vpc_cvdr_axi_wr_resp_err_mask(unsigned int uvpc_cvdr_axi_wr_resp_err_mask);
int iSetVPC_ERR_INT_MASK_vpc_cvdr_axi_wr_full_mask(unsigned int uvpc_cvdr_axi_wr_full_mask);
int iSetVPC_ERR_INT_MASK_vpc_cvdr_vp_wr_dropped_mask(unsigned int uvpc_cvdr_vp_wr_dropped_mask);
int iSetVPC_ERR_INT_MASK_vpc_rdma_axi_rd_resp_err_mask(unsigned int uvpc_rdma_axi_rd_resp_err_mask);
int iSetVPC_ERR_INT_MASK_vpc_rdma_hfbcd_dec_err_mask(unsigned int uvpc_rdma_hfbcd_dec_err_mask);
int iSetVPC_ERR_INT_MASK_STATUS_vpc_s2p_even_width_err_mask_sta(unsigned int uvpc_s2p_even_width_err_mask_sta);
int iSetVPC_ERR_INT_MASK_STATUS_vpc_cvdr_axi_rd_resp_err_mask_sta(unsigned int uvpc_cvdr_axi_rd_resp_err_mask_sta);
int iSetVPC_ERR_INT_MASK_STATUS_vpc_cvdr_axi_wr_resp_err_mask_sta(unsigned int uvpc_cvdr_axi_wr_resp_err_mask_sta);
int iSetVPC_ERR_INT_MASK_STATUS_vpc_cvdr_axi_wr_full_mask_sta(unsigned int uvpc_cvdr_axi_wr_full_mask_sta);
int iSetVPC_ERR_INT_MASK_STATUS_vpc_cvdr_vp_wr_dropped_mask_sta(unsigned int uvpc_cvdr_vp_wr_dropped_mask_sta);
int iSetVPC_ERR_INT_MASK_STATUS_vpc_rdma_axi_rd_resp_err_mask_sta(unsigned int uvpc_rdma_axi_rd_resp_err_mask_sta);
int iSetVPC_ERR_INT_MASK_STATUS_vpc_rdma_hfbcd_dec_err_mask_sta(unsigned int uvpc_rdma_hfbcd_dec_err_mask_sta);
int iSetVPC_ERR_INT_CLR_vpc_s2p_even_width_err_clr(unsigned int uvpc_s2p_even_width_err_clr);
int iSetVPC_ERR_INT_CLR_vpc_cvdr_axi_rd_resp_err_clr(unsigned int uvpc_cvdr_axi_rd_resp_err_clr);
int iSetVPC_ERR_INT_CLR_vpc_cvdr_axi_wr_resp_err_clr(unsigned int uvpc_cvdr_axi_wr_resp_err_clr);
int iSetVPC_ERR_INT_CLR_vpc_cvdr_axi_wr_full_clr(unsigned int uvpc_cvdr_axi_wr_full_clr);
int iSetVPC_ERR_INT_CLR_vpc_cvdr_vp_wr_dropped_clr(unsigned int uvpc_cvdr_vp_wr_dropped_clr);
int iSetVPC_ERR_INT_CLR_vpc_rdma_axi_rd_resp_err_clr(unsigned int uvpc_rdma_axi_rd_resp_err_clr);
int iSetVPC_ERR_INT_CLR_vpc_rdma_hfbcd_dec_err_clr(unsigned int uvpc_rdma_hfbcd_dec_err_clr);
int iSetVPC_ERR_INT_SET_vpc_s2p_even_width_err_set(unsigned int uvpc_s2p_even_width_err_set);
int iSetVPC_ERR_INT_SET_vpc_cvdr_axi_rd_resp_err_set(unsigned int uvpc_cvdr_axi_rd_resp_err_set);
int iSetVPC_ERR_INT_SET_vpc_cvdr_axi_wr_resp_err_set(unsigned int uvpc_cvdr_axi_wr_resp_err_set);
int iSetVPC_ERR_INT_SET_vpc_cvdr_axi_wr_full_set(unsigned int uvpc_cvdr_axi_wr_full_set);
int iSetVPC_ERR_INT_SET_vpc_cvdr_vp_wr_dropped_set(unsigned int uvpc_cvdr_vp_wr_dropped_set);
int iSetVPC_ERR_INT_SET_vpc_rdma_axi_rd_resp_err_set(unsigned int uvpc_rdma_axi_rd_resp_err_set);
int iSetVPC_ERR_INT_SET_vpc_rdma_hfbcd_dec_err_set(unsigned int uvpc_rdma_hfbcd_dec_err_set);
int iSetVPC_BUS_CTRL_1_cfg_awaddr_ext(unsigned int ucfg_awaddr_ext);
int iSetVPC_BUS_CTRL_2_cfg_araddr_ext(unsigned int ucfg_araddr_ext);
int iSetVPC_BUS_CTRL_3_cfg_awuser_l(unsigned int ucfg_awuser_l);
int iSetVPC_BUS_CTRL_4_cfg_awuser_m(unsigned int ucfg_awuser_m);
int iSetVPC_BUS_CTRL_5_cfg_awuser_h(unsigned int ucfg_awuser_h);
int iSetVPC_BUS_CTRL_6_cfg_aruser_l(unsigned int ucfg_aruser_l);
int iSetVPC_BUS_CTRL_7_cfg_aruser_m(unsigned int ucfg_aruser_m);
int iSetVPC_BUS_CTRL_8_cfg_aruser_h(unsigned int ucfg_aruser_h);
int iSetVPC_BUS_CTRL_9_cfg_arqos_en(unsigned int ucfg_arqos_en);
int iSetVPC_BUS_CTRL_9_cfg_awqos_en(unsigned int ucfg_awqos_en);
int iSetVPC_BUS_CTRL_9_cfg_arqos(unsigned int ucfg_arqos);
int iSetVPC_BUS_CTRL_9_cfg_awqos(unsigned int ucfg_awqos);
int iSetVPC_BUS_CTRL_9_cfg_arcache(unsigned int ucfg_arcache);
int iSetVPC_BUS_CTRL_9_cfg_awcache(unsigned int ucfg_awcache);
int iSetVPC_BUS_CTRL_10_cfg_shim_ctrl(unsigned int ucfg_shim_ctrl);
int iSetVPC_RDMA_DEBUG_1_hfbcd_debug_out1(unsigned int uhfbcd_debug_out1);
int iSetVPC_RDMA_DEBUG_2_hfbcd_debug_out2(unsigned int uhfbcd_debug_out2);
int iSetVPC_LINEBUF_DEBUG_1_linebuf_debug_info1(unsigned int ulinebuf_debug_info1);
int iSetVPC_LINEBUF_DEBUG_2_linebuf_debug_info2(unsigned int ulinebuf_debug_info2);
int iSetVPC_LINEBUF_DEBUG_3_linebuf_debug_info3(unsigned int ulinebuf_debug_info3);
int iSetVPC_LINEBUF_DEBUG_4_linebuf_debug_info4(unsigned int ulinebuf_debug_info4);
int iSetVPC_CMDLST_DEBUG_cmdlst_debug_out(unsigned int ucmdlst_debug_out);
int iSetVPC_SP_RAM_CTRL_sp_ram_ctrl(unsigned int usp_ram_ctrl);
int iSetVPC_TP_RAM_CTRL_tp_ram_ctrl(unsigned int utp_ram_ctrl);

#endif // __VPC_TOP_NMANAGER_C_UNION_DEFINE_H__
